1. Field of the Invention
The present invention relates to an erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory. In particular, the present invention relates to an EEPROM (electrically erasable and programmable read-only memory) capable of suppressing threshold-voltage variations among memory cells and preventing soft-writing (erroneous writing) in memory cells, semiconductor integrated circuit device having the EEPROM and a method of manufacturing such an EEPROM.
2. Description of the Prior Art
Semiconductor memories are roughly classified into RAMs (random-access memories) and ROMs (read-only memories). The RAMs allow to rewrite information stored therein at any time. The ROMs allow to write information into them during manufacturing or after manufacturing, and the information once written therein is completely unable to rewrite or is difficult to rewrite. Generally, the RAMs are volatile memories that hold information only with the supply of electric power, and the ROMs are nonvolatile memories that hold information even without power supply.
The ROMs include masked ROMs, EPROMs (erasable and programmable read-only memories), EEPROMs, etc. The EEPROMs are one of the promising semiconductor memories because they are electrically erasable and programmable by the user. Among the EEPROMs, NAND-type EEPROMs have a possibility of replacing magnetic disks because they may have very small memory cells to realize high integration and large capacity.
However, the NAND-type EEPROMs have some problems.
Memory cells of the EEPROM are made of insulated-gate FETs (field effect transistors), and the threshold voltages of these FETs vary from one to another due to variations in the thicknesses of gate insulation films and variations in the concentrations of impurities in channel regions. These variations are produced during the manufacturing of the EEPROM. The threshold-voltage variations reduce a margin in determining whether information read out of a given cell is "0" or "1" and may cause a read error.
The EEPROMs frequently employ a trench structure as an element isolating region between memory cells, to realize high integration and large capacity. The trench structure is composed of a trench formed from the surface of a substrate in the depth direction and insulating material filled in the trench. In a read operation of an insulated-gate FET serving as a memory cell, a read voltage is applied to a control gate electrode of the FET. The read voltage may cause an electric field concentration at a corner of the trench that defines the width of a channel region. During the read operation, the electric field concentration gradually accumulates a charge by injecting electrons from the channel region into a floating gate electrode through a tunnel insulation film, thereby causing soft-writing (erroneous writing).